Novel Quantum Structure of an III-V Tunneling Field-Effect Transistor with Source and Channel Heterojunction
DOI:
https://doi.org/10.15628/holos.2020.8378Palavras-chave:
III-V material, source heterojunction, channel heterojunction, Tunneling field-effect transistor (TFET).Resumo
In this work, an III-V tunneling field-effect transistor (TFET) with source and channel heterojunctions is proposed and introduced. Proposed structure combine the high tunneling efficiency induced by heterojunction material and the high mobility of III-V material. The III-V TFETs based on either source heterojunction and channel heterojunctions have been intensively researched due to their excellent subthreshold-swing characteristics. However, compared with conventional III-V TFETs, the III-V TFETs with source and channel heterojunctions have both shorter tunneling distance and two transmission resonances that significantly improve the on-current. The transfer characteristics affected by gate length were also evaluated. The results show that on-current, off-current, and on-current/off-current ratio and subthreshold-swing of III-V TFETs with source and channel heterojunctions are about 10-3 A/?m, 10-13 A/?m, 10-10 and 30 mV/decade, respectively.Downloads
Referências
Alper, C., Padilla, J. L., Palestri, P., & Ionescu, A. M. (2018). A Novel Reconfigurable Sub-0.25-V Digital Logic Family Using the Electron-Hole Bilayer TFET. IEEE Journal of the Electron Devices Society, 6, 2-7.
Ameen, T. A., Ilatikhameneh, H., Fay, P., Seabaugh, A., Rahman, R., & Klimeck, G. (2019). Alloy Engineered Nitride Tunneling Field-Effect Transistor: A Solution for the Challenge of Heterojunction TFETs. IEEE Transactions on Electron Devices, 66(1), 736-742.
Ashita, Loan, S. A., & Rafat, M. (2019). Insights Into the Impact of Pocket and Source Elevation in Vertical Gate Elevated Source Tunnel FET Structures. IEEE Transactions on Electron Devices, 66(1), 752-758.
Atlas - Device Simulation Framework. (2018). http://www.silvaco.com/products/device_simulation/atlas.html
Chang, H., Adams, B., Chien, P., Li, J., & Woo, J. C. (2013). Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing. IEEE Transactions on Electron Devices, 60(1), 92-96.
Das, G. D., Mishra, G. P., & Dash, S. (2018). Impact of source-pocket engineering on device performance of dielectric modulated tunnel FET. Superlattices and Microstructures, 124, 131-138.
Das, T., Jang, H., Bok Lee, J., Chu, H., Dae Kim, S., & Ahn, J. (2015). Vertical field effect tunneling transistor based on graphene-ultrathin Si nanomembrane heterostructures. 2D Materials, 2(4), 044006.
Dashtbayazi, M., Sabaghi, M., & Marjani, S. (2015). Dynamic comparator with using negative resistance and CMOS input pair strategies in FS =4MHz-10GHz. Journal of Electrical and Electronic Engineering, 3(4), 93–96.
Dorostkar, B., & Marjani, S. (2018). DC ANALYSIS OF p-n-p-n TUNNELING FIELD-EFFECT TRANSISTOR BASED ON In0.35Ga0.65As. HOLOS, 1, 288-296.
Ganapathi, K., Yoon, Y., & Salahuddin, S. (2010). Analysis of InAs vertical and lateral band-to-band tunneling transistors: Leveraging vertical tunneling for improved performance. Applied Physics Letters, 97(3), 033504.
Horst, F., Farokhnejad, A., Zhao, Q., Iniguez, B., & Kloes, A. (2019). 2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs. IEEE Transactions on Electron Devices, 66(1), 132-138.
Ionescu, A. M., & Riel, H. (2011). Tunnel field-effect transistors as energy-efficient electronic switches. Nature, 479(7373), 329-337.
Jain, P., Prabhat, V., & Ghosh, B. (2015). Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material. Journal of Computational Electronics, 14(2), 537-542.
Luisier, M., & Klimeck, G. (2010). Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling. Journal of Applied Physics, 107(8), 084507.
Marjani, S., & Hosseini, S. E. (2014). Radio-frequency modeling of square-shaped extended source tunneling field-effect transistors. Superlattices and Microstructures, 76, 297-314.
Marjani, S., & Hosseini, S. E. (2014). A novel double gate tunnel field effect transistor with 9 mV/dec average subthreshold slope. 2014 22nd Iranian Conference on Electrical Engineering (ICEE).
Marjani, S., & Hosseini, S. E. (2015). Radio-frequency small-signal model of hetero-gate-dielectric p-n-p-n tunneling field-effect transistor including charge conservation capacitance and substrate parameters. Journal of Applied Physics, 118(9), 095708.
Marjani, S., & Hosseini, S. E. (2015). Analysis of radio frequency and stability performance on double-gate extended source tunneling field-effect transistors. 2015 23rd Iranian Conference on Electrical Engineering.
Marjani, S., Hosseini, S. E., & Faez, R. (2016). A 3D analytical modeling of tri-gate tunneling field-effect transistors. Journal of Computational Electronics, 15(3), 820-830.
Marjani, S., Hosseini, S. E., & Faez, R. (2016). A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio. AIP Advances, 6(9), 095010.
Marjani, S., Khosroabadi, S., & Sabaghi, M. (2016). A High Efficiency Ultrathin CdTe Solar Cell for Nano-Area Applications. Optics and Photonics Journal, 06(02), 15-23.
Marjani, S., Khosroabadi, S., & Ebrahim Hosseini, S. (2017). Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer. Oriental Journal of Chemistry, 33(3), 1083-1089.
Noor, S. L., Safa, S., & Khan, M. Z. (2017). A silicon-based dual-material double-gate tunnel field-effect transistor with optimized performance. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 30(6), e2220.
Sabaghi, M., Marjani, S., & Majdabadi, A. (2016). The design of ultra-low power adder cell in 90 and 180 nm CMOS technology. Circuits and Systems, 7(2), 58–67.
Sabaghi, M., Marjani, S., & Majdabadi, A. (2016). A low phase noise, low power and wide tuning range VCO with filtering technique in ISM band. Circuits and Systems, 7(2), 51–57.
Vallett, A. L., Minassian, S., Kaszuba, P., Datta, S., Redwing, J. M., & Mayer, T. S. (2010). Fabrication and Characterization of Axially Doped Silicon Nanowire Tunnel Field-Effect Transistors. Nano Letters, 10(12), 4813-4818.
Woo, S., & Kim, S. (2019). Covered Source–Channel Tunnel Field-Effect Transistors With Trench Gate Structures. IEEE Transactions on Nanotechnology, 18, 114-118.