DC ANALYSIS OF p-n-p-n TUNNELING FIELD-EFFECT TRANSISTOR BASED ON In0.35Ga0.65As

Behnam Dorostkar; Saeid Marjani

doi:10.15628/holos.2018.6173

Autores

Behnam Dorostkar Iran University of Science and Technology, Tehran, Iran http://orcid.org/0000-0003-2410-7235
Saeid Marjani Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran http://orcid.org/0000-0002-2993-7396

DOI:

https://doi.org/10.15628/holos.2018.6173

Palavras-chave:

Analytical model, semiconductor materials, Tunneling field-effect transistor, ON current, OFF current

Resumo

Using calibrated simulations, we report the In_0.35Ga_0.65As based tunnel field-effect transistor (TFET) with thin ?-doped n⁺ pocket at the source-channel interface to improve the parameters such as on current (I_on), off-current (I_off) and subthreshold swing (SS). The simulations results of proposed device is compared with analytical model that is shown with high precision of DC parameters by examining the effects of III-V semiconductor materials. Furthermore, the influence of pocket doping, pocket width, doping level, effective oxide thickness (EOT), temperature and mole fraction of III-V semiconductor material on device performance have been investigated. The results show that proposed device has a higher ON current(1×10^-5 A/µm) and a steeper subthreshold swing (35 mV/decade) as compared with the conventional TFET. It shows a lot of promise for future scale CMOS technology for low voltage and high frequency application

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Biografia do Autor

Behnam Dorostkar, Iran University of Science and Technology, Tehran, Iran

Iran University of Science and Technology, Tehran, Iran

Saeid Marjani, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

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